The present invention relates to a delay lock loop circuit for providing a desired signal delay amount, a variable delay circuit having the delay lock loop circuit, and a recording signal compensating circuit having this variable delay circuit.
Optical-disk-based high-density recording systems under development include a magneto-optical disk system and a phase change optical disk system. In the latter, information is recorded by changing a recording layer to a crystalline phase or an amorphous phase. Recently trend is a particular emphasis on the development of this phase change optical disk system because of its ease of making the optical head smaller because no magnetic head is used, its ease of realizing direct overwriting by which information can be recorded by a single laser irradiation regardless of the presence or absence of marks on the recording surface, and its ease of increasing the S/N (Signal to Noise) ratio of the reproduction system due to a high signal strength, for example.
In a high-density optical disk system, microscopic mark trains must be recorded in correct positions. In the case of the phase change optical disk, signal recording is pure thermal recording, so that heat control at recording is very important for the correct formation of marks. For example, if a recording-level laser is irradiated for a relatively long time to form a comparatively long mark, the formed mark becomes wider toward its end in the disk radius direction due to the thermal storage effect of the recording film. If such a mark is formed, the edge of the trailing end is offset from an ideal position, resulting in an increased error rate. For this reason, the phase change optical disk system uses continuous pulse trains as a laser for mark formation for the thermal control at recording. Also, it is essential for the phase change optical disk system to perform so-called recording compensation to optimally set not only the pulses synchronized with clock but also the position and width of each mark.
One example of the data recording apparatus which performs such recording compensation is disclosed in Japanese Patent Laid-open No. Hei 10-091961. In this disclosure, recording pulses are generated in which a leading pulse having length 1.5T is followed by a pulse train synchronized with clock, thereby lowering the amount of irradiation in the last half of each mark to prevent its width from getting larger. However, this makes the end portion of each mark thermally unstable, sometimes failing to form marks at correct positions. To prevent this problem from happening, the rising edge position and the falling edge position of pulse are delayed to vary the pulse widths of the leading pulse and the trailing pulse. In the disclosed data recording apparatus, such recording pulse B is obtained by a normal logic circuit and a recording compensation circuit based on a delay element of variable delay amount type.
For a delay element for delaying an input signal, an all-pass filter formed by an LC (inductor and capacitor) or a distribution constant circuit for example is known. The delay element of delay amount variable type includes one in which two or more LC delay elements are connected in series, selecting the output from each element by a selector. The delay element having his configuration can provide a comparatively stable delay amount, but presents a problem of significantly increasing the element unit price as compared with the ICs (Integrated Circuits) based on CMOS (Complementary Metal-Oxide Semiconductor) process if the element itself grows in dimension, thereby requiring a larger packaging area. Also, a method is available in which the delay element of delay amount variable type which can be incorporated in a CMOS IC for example is realized by use of the frequency multiplication capability of PLL (Phase-Locked Loop). This method can solve the problem of the large packaging area by incorporating the delay element in the IC but still presents a problem of the increased cost due to the PLL incorporation.
On the other hand, developed with application to digital integrated circuits such as gate arrays and embedded arrays in mind is a delay element realized by positively using the signal propagation delay time in CMOS logic by use of a combination of buffers formed by inverter and NAND gate. Such a delay circuit is obtained by connecting delay lines with two steps of inverters connected in series by the number of steps in series so that a desired delay amount is obtained, for example. The delay circuit having this structure can be configured by basic logic elements, so that it can be easily incorporated in a CMOS IC, thereby involving little increase in packaging area and cost. At the same time, the delay amount generated by the gates inside the IC fluctuates as largely as three times depending on the fluctuations in temperature and supply voltage and the process conditions for example.
For the purpose of solving the above-mentioned problems of CMOS-logic-based delay circuits, a variable delay circuit is disclosed in Japanese Patent Laid-open No. Hei 2000-134072 in which a delay lock loop circuit is used to adjust the number of delay line steps for obtaining a delay amount for 1T. Now, referring to FIG. 15, there is shown a block diagram illustrating an exemplary configuration of a delay lock loop circuit used in the disclosed variable delay circuit.
A delay lock loop circuit 40 shown in FIG. 15 includes a divider 41 for dividing an input pulse into a predetermined frequency and outputting the resultant pulse, a delay line 42 capable of providing a desired delay amount by varying the number of delay steps, a delay amount detector 43 for determining which of input pulses has come first and, on the basis of the decision, outputting a control signal, an up/down counter (hereafter referred to as a U/D counter) 44 for controlling the number of delay steps in the delay line 42 in accordance with this control signal, and a delay lock detector 45 for outputting the number of delay steps which provide the amount of delay of 1T provided by the delay line 42 with reference to the output signal of the U/D counter 44.
The divider 41 generates data pulse TP of 1T obtained by dividing inputted clock CLK by 2, data pulse TP2 of 2T obtained by dividing CLK by 4, and data pulse TP4 of 4T obtained by dividing CLK by 8. The delay line 42 is a signal delay circuit which is formed by two inverters for example connected in series which are connected in series by the required number of steps, thereby providing variable delay amounts. With count value SEL of the U/D counter 44 used as the setting data for the number of delay steps, the delay line 42 delays, by 1T, data pulse TP supplied from the divider 41. The delay amount detector 43 outputs, on the basis of data pulse DTP delayed by the delay line 42 and data pulse TP2 supplied from the divider 41, an up/down control signal (hereafter referred to as a U/D control signal) UD for controlling the count-up and count-down operations of the U/D counter 44.
Referring FIG. 16, there is shown a circuit diagram illustrating an exemplary circuit configuration of the delay amount detector 43.
The delay amount detector 43 includes a D flip-flop (hereafter referred to as a D-FF) 431 forming an input stage, an exclusive OR gate (hereafter referred to as an EOR gate) 432, an inverter 433, and a D-FF 434 forming an output stage. In this delay amount detector 43, the D-FF 431 latches data pulse TP2 supplied from the divider 41 on the basis of data pulse DTP outputted from the delay line 42 to determine which of the rising of data pulse DTP delayed by 1T by the delay line 42 and the inversion of data pulse TP2 providing reference of timing for delay amount 1T has come first. On the basis of the result of the decision, the delay amount detector 43 outputs, from the D-FF 434, a U/D control signal UD as a control signal for selecting the increase or decrease in the number of delay steps. The outputted U/D control signal UD is logically high if the rising of data pulse TP2 is earlier than the rising of data pulse DTP and logically low if otherwise.
Returning to FIG. 15, on the basis of the U/D control signal UD from the delay amount detector 43, the U/D counter 44 counts up or down the number of delay steps and outputs count value SEL, thereby controlling the number of delay steps for delay amount 1T given by the delay line 42. The delay lock detector 45 makes comparison between the number of delay steps at the current point of time, the number of delay steps one clock before, and the number of delay steps two clocks before in a timed relation with data pulse TP4 from the divider 41 and on the basis of count value SEL from the U/D counter 44, thereby outputting delay lock signal LOCK indicative of whether or not the number of delays steps is locked and reference delay step count DREF for obtaining 1T delay by the delay line 42. Now, in relation to the current number of delay steps, namely current count value SEL from the U/D counter 44, let the number of delay steps one clock before and two clocks before of data pulse TP4, which is clock input CK, be SEL1 and SEL2 respectively, then, if SEL=SEL2, delay clock signal LOCK is logically high; otherwise, it is logically low. If SEL=SEL2 or if SEL greater than SEL1, then SEL1 is outputted as reference delay step count DREF; otherwise, current count value SEL is outputted.
Referring to FIG. 17, there is shown a timing chart indicative of the behaviors of various signals in the delay lock loop circuit 40.
As shown in FIG. 17, in a period between 900 ns and 1100 ns, the delay amount due to the gate constituting the delay line 42 fluctuates due to the fluctuations in temperature and supply voltage for example. At this moment, because the delay amount due to count value SEL indicative of the number of delay steps in the delay line 42 falls short for the delay for 1T, count value SEL from the U/D counter 44 and reference delay step count DREF are each counted up by one 1, turning delay lock signal LOCK logically low.
In 1100 ns timing, the inverted timing of data pulse TP2 inputted in the delay amount detector 43 becomes earlier than the rising of data pulse DTP and therefore the U/D control signal UD to be outputted goes logically low, thereby counting down count value SEL of the U/D counter 44. Subsequently, at the rising of data pulse TP4, the U/D control signal UD alternately repeats logically high and logically low, causing count value SEL of the U/D counter 44 to take xe2x80x9c29xe2x80x9d and xe2x80x9c28xe2x80x9d alternately. In 1050 ns timing, the delay lock detector 45 detects a match in xe2x80x9c29xe2x80x9d between current count value SEL and count value SEL2 two clocks before based on data pulse TP4, causing delay lock signal LOCK to go logically high. Consequently, the value of reference delay step count DREF delayed by 1T by the delay line 42 is fixed to xe2x80x9c28,xe2x80x9d thereby locking the operation of the delay lock loop circuit 40.
In the above-mentioned variable delay circuit based on the delay lock loop circuit 40, the ratio of a delay amount to the width of 1T pulse is set as required, the ratio is multiplied with the value of reference delay step count DREF, and the multiplication result is set as a delay setting step count to a delay line configured in the same manner as the delay line 42, thereby delaying the inputted data pulse. Consequently, the variable delay circuit based on the delay lock loop circuit 40 is able to always provide desired delay amounts even if the amount of delay by the gate forming a delay line is varied due to the fluctuation in temperature and supply voltage, regardless of the amount of the variation. Therefore, in the above-mentioned phase change optical disk system, the above-mentioned variable delay circuit is used to correctly delay, by a desired amount, the rising position at the leading end of a recording pulse and the falling position at the trailing end, thereby correctly controlling the outline of each mark formed on the disk.
In the above-mentioned delay lock loop circuit 40 overcomes the defects of the delay line caused by the CMOS gate and provides delay amounts at low cost and with stability, thereby being realized as an IC for the recording compensation for optical disk drives. However, in the actual operation by the delay lock loop circuit 40, a phenomenon is observed that count value SEL outputted from the U/D counter 44 is not plus/minus 1 step even in a state where reference delay step count DREF is almost stable, thereby repeating an irregular variation with a width of several steps.
Referring to FIG. 18, there is shown a timing chart indicative of the timings of various signals in the delay lock loop circuit 40 which are observed if the above-mentioned abnormal operation takes place.
As shown in FIG. 18, a period up to 1670 ns, reference delay step count DREF is locked to xe2x80x9c28.xe2x80x9d However, at timings of 1670 ns, 1770 ns, and 1870 ns, the U/D control signal UD becomes logically high, continuously counting up count value SEL. Hence, by the detection by the delay lock detector 45, delay lock signal LOCK goes logically low. Subsequently, count value SEL is counted up to value xe2x80x9c2bxe2x80x9d and counted down to value xe2x80x9c28,xe2x80x9d thereby locking the operation of the delay lock loop circuit 40 again at timing of 2250 ns.
The above-mentioned irregular variation of reference delay step count DREF is thought of as due to the D-FF 431 used in the delay amount detector 43. In the timing comparison in the delay amount detector 43, Q output namely phase comparison intermediate signal QA is outputted on the basis of which of the rising of data pulse DTP of clock input CK in the D-FF 431 and the inversion of data pulse TP2 of data input D takes place first, executing an exclusive OR operation between phase comparison intermediate signal QA and data pulse TP2 in the EOR gate 432 to output phase comparison signal UP. However, if the rising of clock input CK and the inversion of data input D in the D-FF 431 are inputted successively in a time shorter than the minimum setup time and hold time of the D-FF 431, phase comparison intermediate signal QA to be inputted is not settled, thereby causing a short-period disturbance in the outputted U/D control signal UD.
It should be noted that the case in which the rising of clock input CK and the inversion of data input D take place substantially at the same time denotes that the delay amount between data pulse TP and data pulse DTP due to the delay line 42 matches 1T. In the delay lock loop circuit 40, control is executed so that above-mentioned state is always maintained, so it is assumed that the state in which phase comparison intermediate signal QA is unstable takes place at a high rate when the operation of the delay lock loop circuit 40 is almost locked. The U/D control signal UD at the timings of 1770 ns and 1870 ns shown in FIG. 18 is thought of as a noise component that takes place in the above-mentioned case. This noise component irregularly varies count value SEL of the U/D counter 44 without counting up and down alternately; consequently the value of reference delay step count DREF is not locked, being varied without stability with a magnitude of plus/minus several steps.
Consequently, with the variable delay circuit based on the delay lock loop circuit 40, in setting the number of delay steps in a delay line, if reference delay step count DREF is multiplied by xc2xd to obtain a delay of T/2, reference delay step count DREF does not become constant, so that a jitter is generated in the output signal of the delay line.
It is therefore an object of the present invention to provide a delay lock loop circuit for providing stable delay amounts regardless of the variation in delay amount due to the fluctuation in temperature and supply voltage and process conditions if a delay circuit which is low in cost and small in packaging area is used in this delay lock loop circuit.
It is another object of the present invention to provide a variable delay circuit based on a delay circuit which is low in cost and small in packaging area for providing stable delay amounts regardless of the variation in delay amount due to the fluctuation in temperature and supply voltage and process conditions.
It is still another object of the present invention to provide a recording signal compensating circuit based on a delay circuit which is low in cost and small in packaging area for correctly delaying recording pulses when recording data to a disk storage medium.
According to the first aspect of the present invention, there is provided a delay lock loop circuit including:
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data;
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, the sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of the third pulse data and, when the count value has reached the maximum value and the minimum value, setting a next count value to the initial value, the up/down counter executing a count-up operation at a rising edge of the third pulse data when the count value of the sub counter is the maximum value and a count-down operation when the count value is the minimum value;
a delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter;
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal; and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count.
According to the second aspect of the present invention, there is provided A variable delay circuit including:
a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data,
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, the sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of the third pulse data and, when the count value has reached the maximum value and the minimum value, setting a next count value to the initial value, the up/down counter executing a count-up operation at a rising edge of the third pulse data when the count value of the sub counter is the maximum value and a count-down operation when the count value is the minimum value,
a first delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter,
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the first delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which the clock signal is supplied, for multiplying the reference delay step count with a delay rate; and
a second delay means, configured in substantially a same manner as the first delay means, for delaying inputted data on the basis of a delay step count set by the delay step count setting means.
According to the third aspect of the present invention, there is provided A recording signal compensating circuit for recording data to a disk recording medium in accordance with a recording pulse obtained by synthesizing a leading pulse, a burst pulse, and a trailing pulse, including:
a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data,
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, the sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of the third pulse data and, when the count value has reached the maximum value and the minimum value, setting a next count value to the initial value, the up/down counter executing a count-up operation at a rising edge of the third pulse data when the count value of the sub counter is the maximum value and a count-down operation when the count value is the minimum value,
a first delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter,
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the first delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means to which the clock signal is supplied, for multiplying the reference delay step count with a delay rate;
a second delay means, configured in substantially a same manner as the first delay means, for delaying inputted data on the basis of a delay step count set by the delay step count setting means;
a leading pulse varying means for varying a pulse width of the leading pulse by delaying a leading edge position of the leading pulse; and
a trailing pulse varying means for varying a pulse width of the trailing pulse by delaying a trailing edge position of the trailing pulse.
According to the fourth aspect of the present invention, there is provided A delay lock loop circuit including:
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data;
an up/down counter having
a first counter for executing a count-up operation at a rising edge of the third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting the count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted, and
a third counter for executing a count-up operation only when the up/down control signal is logically low at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted,
the up/down counter executes, when the reset signal is inputted, a count/up operation if the count value obtained by the second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by the third counter is higher than the preset value N;
a delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter;
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal; and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count.
According to the fifth aspect of the present invention, there is provided A variable delay circuit including:
a reference delay step count outputting means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data,
an up/down counter having
a first counter for executing a count-up operation at a rising edge of the third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting the count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted, and
a third counter for executing a count-up operation only when the up/down control signal is logically low at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted,
the up/down counter executes, when the reset signal is inputted, a count/up operation if the count value obtained by the second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by the third counter is higher than the preset value N,
a first delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter,
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the first delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which the clock signal is supplied, for multiplying the reference delay step count with a delay rate; and
a second delay means, configured in substantially a same manner as the first delay means, for delaying inputted data on the basis of a delay step count set by the delay step count setting means.
According to the sixth aspect of the present invention, there is provided A recording signal compensating circuit for recording data to a disk recording medium in accordance with a recording pulse obtained by synthesizing a leading pulse, a burst pulse, and a trailing pulse, including:
a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of the first pulse data, and third pulse data having a period greater than that of the second pulse data,
an up/down counter having
a first counter for executing a count-up operation at a rising edge of the third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting the count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted, and
a third counter for executing a count-up operation only when the up/down control signal is logically low at a rising edge of the third pulse data and resetting a count value when the reset signal is inputted,
the up/down counter executes, when the reset signal is inputted, a count/up operation if the count value obtained by the second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by the third counter is higher than the preset value N,
a first delay means for delaying the first pulse data in accordance with the number of delay steps based on a count output of the up/down counter,
a delay amount detecting means for determining which of a rising edge of the second pulse data and a rising edge of an output pulse of the first delay means comes first and outputting, on the basis of a result of this determination, the up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of the up/down counter at a rising edge of the third pulse data to determine whether or not a delay amount is locked, selecting one of the current count value and the past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which the clock signal is supplied, for multiplying the reference delay step count with a delay rate;
a second delay means, configured in substantially a same manner as the first delay means, for delaying inputted data on the basis of a delay step count set by the delay step count setting means;
a leading pulse varying means for varying a pulse width of the leading pulse by delaying a leading edge position of the leading pulse; and
a trailing pulse varying means for varying a pulse width of the trailing pulse by delaying a trailing edge position of the trailing pulse.